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White Electronic Designs
W3HG2128M72ACER-AD6
PRELIMINARY*
2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP
FEATURES
240-pin, dual in-line very low profile (VLP) memory module Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4300 and PC2-3200 Utilizes 800, 667, 533 and 400 Mb/s DDR2 SDRAM components VCC = VCCQ = 1.8V VCCSPD = +1.7V to +3.6V Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture DLL to align DQ and DQS transitions with CK Multiple internal device banks for concurrent operation Supports duplicate output strobe (RDQS/RDQS#) Programmable CAS# latency (CL): 3, 4, 5 and 6 Adjustable data-output drive strength On-die termination (ODT) Posted CAS# additive latency: 0, 1, 2, 3 and 4 Serial Presence Detect (SPD) with EEPROM 64ms: 8,192 cycle refresh Gold edge contacts ECC error detection and correction Dual Rank RoHS compliant Package option * 240 Pin VLP: 18.29mm (0.720") TYP
DESCRIPTION
The W3HG2128M72ACER is a 2x128Mx72 Double Data Rate DDR2 SDRAM high density module based on DDR2 SDRAM components. This memory module consists of eighteen stacks of 256Mx4 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a 240-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to change without notice. NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option * Parity function
OPERATING FREQUENCIES
PC2-3200 Clock Speed CL-tRCD-tRP
* Consult factory for availability
PC2-4300 266MHz 4-4-4
PC2-5300* 333MHz 5-5-5
PC2-6400* 400MHz 6-6-6
200MHz 3-3-3
May 2006 Rev. 5
1
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PIN CONFIGURATION
Pin No. Symbol Pin No. 1 VREF 61 2 VSS 62 3 DQ0 63 4 DQ1 64 5 VSS 65 6 DQS0# 66 7 DQS0 67 8 VSS 68 9 DQ2 69 10 DQ3 70 71 11 VSS 12 DQ8 72 13 DQ9 73 14 VSS 74 15 DQS1# 75 16 DQS1 76 77 17 VSS 18 RESET# 78 19 NC 79 20 VSS 80 21 DQ10 81 22 DQ11 82 83 23 VSS 24 DQ16 84 25 DQ17 85 86 26 VSS 27 DQS2# 87 28 DQS2 88 89 29 VSS 30 DQ18 90 31 DQ19 91 32 VSS 92 33 DQ24 93 34 DQ25 94 95 35 VSS 36 DQS3# 96 37 DQS3 97 38 VSS 98 39 DQ26 99 40 DQ27 100 101 41 VSS 42 CB0 102 43 CB1 103 44 VSS 104 45 DQS8# 105 46 DQS8 106 107 47 VSS 48 CB2 108 49 CB3 109 50 VSS 110 51 VCCQ 111 52 CKE0 112 113 53 VCC 54 NC 114 55 NC/ERR_OUT 115 56 VCCQ 116 57 A11 117 58 A7 118 119 59 VCC 60 A5 120 May 2006 Rev. 5 Symbol A4 VCCQ A2 VCC VSS VSS VCC NC/PAR_IN VCC A10/AP BA0 VCCQ WE# CAS# VCCQ S1# ODT1 VCCQ VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Symbol VSS DQ4 DQ5 VSS DQS9 DQS9# VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DQS10 DQS10# VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DQS11 DQS11# VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS12 DQS12# VSS DQ30 DQ31 VSS CB4 CB5 VSS DQS17 DQS17# VSS CB6 CB7 VSS VCCQ CKE1 VCC NC NC VCCQ A12 A9 VCC A8 A6 Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Symbol VCCQ A3 A1 VCC CK0 CK0# VCC A0 VCC BA1 VCCQ RAS# S0# VCCQ ODT0 A13 VCC VSS DQ36 DQ37 VSS DQS13 NC/DQS13# VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS14 NC/DQS14# VSS DQ46 DQ47 VSS DQ52 DQ53 VSS NC NC VSS DQS15 NC/DQS15# VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS16 NC/DQS16# VSS DQ62 DQ63 VSS VCCSPD SA0 SA1 2
W3HG2128M72ACER-AD6
PRELIMINARY
PIN NAMES
Pin Name A0-A13 BA0,BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 DQS0#-DQS8# DM0-DM8 DQS9#-DQS17# DQS9-DQS17 ODT0, ODT1 CK0,CK0# CKE0, CKE1 S0#, S1# RAS# CAS# WE# RESET# SA0-SA2 SDA SCL VCC VCCQ VSS VREF VCCSPD NC Function Address Inputs SDRAM Bank Address Data Input/Output Check Bits Data strobes Data strobes complement Data Masks Data Strobe Negative Data Strobe On-die termination control Clock Inputs, positive line Clock Enables Chip Selects Row Address Strobe Column Address Strobe Write Enable Register Reset Input SPD address SPD Data Input/Output Serial Presence Detect(SPD) Clock Input Core Power (1.8V) I/O Power (1.8V) Ground Power Supply for Reference SPD Power Spare pins, No connect
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
W3HG2128M72ACER-AD6
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
VSS RS1# RS0# DQS0 DQS0#
DM CS# DQS DQS# DM CS# DQS DQS#
DQS9 DQS9#
DM CS# DQS DQS# DM CS# DQS DQS#
DQ0 DQ1 DQ2 DQ3 DQS1 DQS1# DQ8 DQ9 DQ10 DQ11 DQS2 DQS2#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ4 DQ5 DQ6 DQ7 DQS10 DQS10#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ12 DQ13 DQ14 DQ15 DQS11 DQS11#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ16 DQ17 DQ18 DQ19 DQS3 DQS3#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ20 DQ21 DQ22 DQ23 DQS12 DQS12#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ24 DQ25 DQ26 DQ27 DQS4 DQS4#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ28 DQ29 DQ30 DQ31 DQS13 DQS13#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ32 DQ33 DQ34 DQ35 DQS5 DQS5#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ36 DQ37 DQ38 DQ39 DQS14 DQS14#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ40 DQ41 DQ42 DQ43 DQS6 DQS6#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ44 DQ45 DQ46 DQ47 DQS15 DQS15#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ48 DQ49 DQ50 DQ51 DQS#7 DQS7#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ52 DQ53 DQ54 DQ55 DQS16 DQS16#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ56 DQ57 DQ58 DQ59 DQS8 DQS8#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ60 DQ61 DQ62 DQ63 DQS17 DQS17#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
CB0 CB1 CB2 CB3
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
CB4 CB5 CB6 CB7
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
VCCSPD
S0# S1# BA0-BA1 A0-A13 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 RESET# PCK7** PCK7#**
Serial PD DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs
1:2
R E G I S T E R
RS0# CS# : DDR2 SDRAMs RS1# CS# : DDR2 SDRAMs RBA0-RBA1 BA0-BA1 : DDR2 SDRAMs RA0-RA13 A0-A13 : DDR2 SDRAMs RRAS# RAS# : DDR2 SDRAMs RCAS# CAS# : DDR2 SDRAMs RWE# WE# : DDR2 SDRAMs SCL RCKE0 CKE : DDR2 SDRAMs RCKE1 CKE : DDR2 SDRAMs RODT0 ODT : DDR2 SDRAMs RODT1 ODT : DDR2 SDRAMs
VCC/VCCQ VREF
Serial PD
VSS
SDA
WP A0
A1
A2
SA0 SA1 SA2
RST#
CK0 CK0# RESET#**
P L L
OE
PCK0-PCK6, PCK8, PCK9
CK : DDR2 SDRAMs CK# : DDR2 SDRAMs
PCK0#-PCK6#, PCK8#, PCK9# PCK7 CK : Register PCK7# CK# : Register
NOTE: All resistor values are 22 ohms unless otherwise specified.
May 2006 Rev. 5
3
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All Voltages Referenced to VSS
W3HG2128M72ACER-AD6
PRELIMINARY
RECOMMENDED DC OPERATING CONDITIONS
Rating Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage Symbol VCC VCCL VCCQ VREF VTT Min. 1.7 1.7 1.7 0.49*VCCQ VREF-0.04 Type 1.8 1.8 1.8 0.50*VCCQ VREF Max. 1.9 1.9 1.9 0.51*VCCQ VREF+0.04 Units V V V V V Notes 4 4 4 1, 2 3
There is no specific device VCC supply voltage requirement for SSTL-1.8 compliance. However under all conditions VCCQ must be less than or equal to VCC. 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VCCQ of the transmitting device and VREF is expected to track variations in VCCQ. 2. Peak to peak AC noise on VREF may not exceed 2% VREF(DC). 3. VTT of transmitting device must track VREF of receiving device. 4. VCC, VCCQ and VCCL are tied together on this module.
ABSOLUTE MAXIMUM RATINGS
SSTL_1.8V Symbol VCC VCCQ VCCL VIN, VOUT TSTG Parameter Voltage on VCC pin relative to VSS Voltage on VCCQ pin relative to VSS Voltage on VCCL pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Rating - 1.0 V - 2.3 V - 0.5 V - 2.3 V - 0.5 V - 2.3 V - 0.5 V - 2.3 V -55 to +100 Units V V V V C Notes 5 5 5 5 5, 6
5. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 6. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
CAPACITANCE
TA = 25C, f = VREF = Gnd, f = 100MHz, VCC = VCCQ = 1.8V Parameter Input Capacitance: CK, CK# Input Capacitance: CKE, CS# Input Capacitance: Addr. RAS#, CAS#, WE#, ODT Input/Output Capacitance: DQ, DQS, DM, DQS#, CB Symbol CCK CI1 CI2 CIO Max 5.6 12.4 12.4 15.6 Units pF pF pF pF
May 2006 Rev. 5
4
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W3HG2128M72ACER-AD6
PRELIMINARY
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only Symbol Proposed Conditions ICC0 Operating one bank active-precharge current; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1 806
TBD
665 1,720
534 1,530
403 1,530
Units mA
ICC1
TBD
1,980
1,800
1,710
mA
ICC2P
TBD
180
180
180
mA
ICC2Q
TBD
1,800
1,440
1,260
mA
ICC2N
TBD
1,980 1,260 360
1,620 1,080 360
1,440 900 360
mA mA mA
TBD TBD
ICC3P
ICC3N
Active standby current; All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as ICC4R; Refer to the following page for detailed timing conditions
TBD
2,340
1,980
1,620
mA
ICC4W
TBD
2,880
2,430
2,070
mA
ICC4R
TBD
3,240
2,700
2,160
mA
ICC5B
TBD
7,560
7,200
6,840
mA
ICC6
TBD
180
180
180
mA
ICC7
TBD
5,130
4,770
4,230
mA
NOTE: ICC specs are based on MICRON components. Other DRAM manufacturers parameters may be different.
May 2006 Rev. 5
5
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W3HG2128M72ACER-AD6
PRELIMINARY
AC TIMING PARAMETERS
0C TCASE < +85C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V AC CHARACTERISTICS PARAMETER CL = 6 Clock cycle time Clock CL = 5 CL = 4 CL = 3 CK high-level width CK low-level width Half clock period SYMBOL tCK (6) tCK (5) tCK (4) tCK (3) tCH tCL tHP
TBD TBD
806 MIN
TBD TBD TBD TBD TBD TBD
667 MAX
TBD TBD TBD TBD TBD TBD
534 MAX MIN MAX MIN
403 MAX UNIT ps Notes 16, 24 16, 24 16, 24 16, 24 18 18 19
MIN
3,000 3,750 5,000 0.45 0.45 MIN (tCH, tCL) -450
8,000 8,000 8,000 0.55 0.55 3,750 5,000 0.45 0.45 MIN (tCH, tCL) +450 tAC (MAX) -500 +500 tAC MAX tAC (MIN) 350 350 100 225 0.35 340 400 tHPtQHS tQHtDQSQ 0.35 0.35 +400 -450 0.2 0.2 240 300 0.9 1.1 0.9 +450 tHPtQHS tQHtDQSQ 0.35 0.35 -500 0.2 0.2 350 1.1 +500 tAC (MAX) tAC (MIN) 400 400 150 275 0.35 450 8,000 8,000 0.55 0.55 5,000 5,000 0.45 0.45 MIN (tCH, tCL) -600 +600 tAC MAX tAC (MAX) 8,000 8,000 0.55 0.55
ps ps ps tCK tCK ps
DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS Data DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ...DQS hold, DQS to first DQ to go nonvalid, per access relative to DQS Data hold skew factor DQ-DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# Data Strobe DQS falling edge to CK rising- setup time DQS falling edge from CK rising - hold time DQS-DQ skew, DQS to last DQ valid, per group, per access DQS read preamble
tAC tHZ tLZ tDSa tDHa tDSb tQHb tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS
TBD TBD
TBD TBD
ps ps ps ps ps tCK ps ps 8, 9 8, 10 7, 15, 21 7, 15, 21 7, 15, 21 7, 15, 21
TBD
TBD
tAC (MIN) 300 300 100 175 0.35
tAC (MAX)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD TBD TBD
TBD TBD TBD
tHPtQHS tQHtDQSQ 0.35 0.35 -400 0.2
15, 17 15, 17 tCK tCK ps tCK tCK ps tCK 15, 17 35
TBD TBD TBD TBD
TBD TBD TBD TBD
TBD
TBD
tDSH
TBD TBD
0.2
tDQSQ
TBD TBD
tRPRE
TBD
TBD
0.9
1.1
NOTE: * AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
May 2006 Rev. 5 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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W3HG2128M72ACER-AD6
PRELIMINARY
AC TIMING PARAMETERS (Continued)
0C TCASE < +85C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V AC CHARACTERISTICS PARAMETER DQS read preamble Data Strobe DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition Address and control input pulse width for each input Address and control input setup time Address and control input hold time Address and control input setup time Address and control input hold time CAS# to CAS# command delay Active to Active (same bank) command Active bank a to Active b bank command Active to Read or Write delay Four Bank Activate period Active to precharge command Internal Read to precharge command delay Write recovery time Auto precharge write recovery and precharge time Interval Write to Read command delay Precharge command period Precharge All command period Load Mode command cycle time CKE low to CK,CK# uncertainty SYMBOL tRPST tWPRES tWPRE tWPST tDQSS tIPW tISa tIHa tISb tIHb tCCD tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD tDELAY MIN
TBD TBD TBD TBD TBD
806 MAX
TBD TBD TBD TBD TBD
665 MIN 0.4 0 0.35 0.4 WL0.25 0.6 400 400 200 275 2 55 7.5 15 37.5 40 7.5 15 tWR+tRP 10 15 tRP+tCK 2 tIS+tCK+tIH 70,000 0.6 MAX 0.6 MIN 0.4 0 0.25 0.4 WL0.25 0.6 500 500 250 375 2 55 7.5 15 37.5 40 7.5 15
534 MAX 0.6 MIN 0.4 0 0.25 0.6 0.4 WL0.25 0.6 600 600 350 475 2 55 7.5 15 37.5 70,000 40 7.5 15
403 MAX 0.6 UNIT tCK ps tCK 0.6 tCK tCK tCK ps ps ps ps tCK ns ns ns ns 70,000 ns ns ns ns ns ns ns tCK tIS+tCK+tIH ns 28 30 20, 33 23, 27 27 22 27 31 31 33 27 6, 21 6, 21 6, 21 6, 21 11 Notes 35 12, 13, 36
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Command and Address
TBD TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD TBD
tWR+tRP 7.5 15 tRP+tCK 2 tIS+tCK+tIH
tWR+tRP 10 15 tRP+tCK 2
TBD TBD TBD TBD
TBD TBD TBD TBD
TBD
TBD
NOTE: * AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
May 2006 Rev. 5
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W3HG2128M72ACER-AD6
PRELIMINARY
AC TIMING PARAMETERS (Continued)
0C TCASE < +85C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V AC CHARACTERISTICS PARAMETER Refresh to Active or Refresh to Refresh command interval Self Refresh Average periodic refresh interval Exit self refresh to non-read command Exit self refresh to read command Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off ODT ODT turn-on (power-down mode) ODT turn-off (power-down mode) ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Power-Down Exit active power-down to READ command, MR[bit12=1] Exit precharge power-down to any non-READ command. CKE minimum high/low time SYMBOL tRFC (2GB) tRFC (4GB) tREFI tXSNR tXSRD tISXR tAOND tAON tAOFD tAOF MIN
TBD TBD TBD
806 MAX
TBD TBD TBD
665 MIN 105 127.5 200 tRFC
(MIN)+10
534 MAX 70,000 70,000 7.8 tRFC
(MIN)+10
403 MAX 70,000 70,000 7.8 tRFC
(MIN)+10
MIN 105 127.5
MIN 105 127.5
MAX 70,000 70,000 7.8
UNIT ns ns s ns tCK ps
Notes 14 14 14
TBD
TBD
TBD
TBD
200 tIS 2 tAC(MIN) 2.5 tAC(MIN)
tAC(MIN)
200 tIS 2 tAC(MAX) +700 2.5 tAC(MAX) +600
2x tCK + tAC (MAX) + 1,000 2x tCK + tAC (MAX) + 1,000
200 tIS 2 tAC(MAX) +1,000 2.5 tAC(MAX) +600
2x tCK + tAC (MAX) + 1,000 2x tCK + tAC (MAX) + 1,000
TBD TBD
TBD TBD
6, 29
2 tAC(MIN) 2.5 tAC(MIN)
tAC(MIN) +2,000 tAC(MIN) +2,000
2 tAC(MIN) 2.5 tAC(MIN)
tAC(MIN) +2,000 tAC(MIN) +2,000
2 tAC(MAX) +1,000 2.5 tAC(MAX) +600
2x tCK + tAC (MAX) + 1,000 2x tCK + tAC (MAX) + 1,000
tCK ps tCK ps 26 25
TBD
TBD
TBD
TBD
TBD
TBD
tAONPD
TBD
TBD
+2,000 tAC(MIN)
ps
tAOFPD tANPD tAXPD tXARD tXARDS tXP tCKE
TBD
TBD
+2,000
tCK tCK tCK tCK tCK tCK tCK 34
TBD TBD TBD
TBD TBD TBD
3 8 2 7-AL 2 3
3 8 2 6-AL 2 3
3 8 2 6-AL 2 3
TBD
TBD
TBD TBD
TBD TBD
NOTE: * AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
May 2006 Rev. 5
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Notes
1. 2. All voltages referenced to VSS Tests for AC timing, ICC, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. Outputs measured with equivalent load: 13.
VTT = VCCQ/2 25 Output (VOUT) Reference Point
W3HG2128M72ACER-AD6
PRELIMINARY
High-Z and that any signal transition within the input switching region must follow valid input requirements. That is if DQS transitions high (above VIH DC (MIN) then it must not transition low (below VIH (DC) prior to tDQSH (MIN). 12. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turn around. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. The refresh period is 64ms. This equates to an average refresh rate of 7.8125s. However, a REFRESH command must be asserted at least once every 70.3s or tRFC (MAX). To ensure all rows of all banks are properly refreshed, 8192 REFRESH commands must be issued every 64ms. Each half-byte lane has a corresponding DQS. CK and CK# input slew rate must be 1V/ns ( 2V/ns if measured differentially). The data valid window is derived by achieving other specifications - tHP. (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. This value can be greater than the minimum specification limits for tCL and tCH. For example, tCL and tCH are = 50 percent of the period, less the half period jitter [tJIT(HP)] of the clock source, and less the half period jitter due to cross talk [tJIT(cross talk)] into the clock traces. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs. READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) is satisfied since tRAS lockout feature is supported in DDR2 SDRAM devices. VIL/VIH DDR2 overshoot/undershoot. REFER to the 512Mb or 1Gb DDR2 SDRAM data sheet for more detail. tDAL = (nWR) + (tRP/tCK): For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period; nWR refers to the tWR parameter stored in the MR[11,10,9]. Example: For 534 at tCK= 3.75 ns with tWR programmed to four clocks. tDAL = 4 + (15 ns/3.75ns) clock = 4 + (4) clocks = 8 clocks. The minimum READ to internal PRECHARGE time. This parameter is only applicable when tRTP/2*tCK) > 1. If tRTP/2*tCK) 1, then equation AL + BL/2 applies. Notwithstanding, tRAS (MIN) has to be satisfied as well. The DDR2 SDRAM device will automatically delay the internal PRECHARGE command until tRAS (MIN) has been satisfied. Operating frequency is only allowed to change during self refresh mode, precharge power-down mode, and system reset condition. ODT turn-on time tAON (MIN) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn-on time tAON (MAX) is when the ODT resistance is fully on. Both are measured from tAOND.
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
3.
4.
AC timing and ICC tests may use a VIL to VIH swing of up to 1.0V in the test environment parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1.0V/ns for signals in the range between VIL (AC) and VIH (AC). Slew derates less than 1.0V/ns require the timing parameters to be rated as specified. The AC and DC input level specifications are as defined in the SSTL_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). Command/Address minimum input slew rate is at 1.0V/ns. Command/Address input timing must be derated if the slew rate is not 1.0V/ns. This is easily accommodated using tISb and the Setup and Hold Time Derating Values table. tIS timing (tISb) is referenced from VIH (AC) for a rising signal and VIL (AC) for a falling signal. tIH timing (tIHb) is referenced from VIH (AC) for a rising signal and VIL (DC) for a falling signal. The timing table also lists the tISb and tIHb values for a 1.0V/ns slew rate; these are the "base" values. Data minimum input slew rate is at 1.0V/ns. Data input timing must be derated if the slew rate is not 1.0V/ns. This is easily accommodated if the timing is referenced from the logic trip points. tDS timing (tDSb) is referenced from VIH (AC) for a rising signal and VIL (AC) for a falling signal. tIH timing (tIHb) is referenced from VIH (DC) for a rising signal and VIL (DC) for a falling signal. The timing table lists the tDSb and tDHb values for a 1.0V/ns slew rate. If the DQS/DQS# differential strobe feature is not enabled, timing is no longer referenced to the cross point of DQS/DQS#. Data timing is now referenced to VREF, provided the DQS slew rate is not less than 1.0V/ns. If the DQS slew rate is less than 1.0V/ns, then data timing is now referenced to VIH (AC) for a rising DQS and VIL (DC) for a falling DQS. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (when the device output is no longer driving (tHZ) or begins driving (tLZ). This maximum value is derived from the referenced test load. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) tLZ will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition. The intent of the Don't Care state after completion of the postamble is the DQS-driven signal should either be high, low or
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May 2006 Rev. 5
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White Electronic Designs
26. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time tAOF (MAX) is when the bus is in high impedance. Both are measured from tAOFD. This parameter has a two clock minimum requirement at any tCK. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed prior to CK, CK# being removed in a system RESET condition. tISXR is equal to tIS and is used for CKE setup time during self refresh exit. No more than 4 bank ACTIVE commands may be issued in a given tFAW (MIN) period. tRRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies to all 8 bank DDR2 devices, regardless of the number of banks already open or closed. tRPA timing applies when the PRECHARGE(ALL) command is issued, regardless of the number of banks already open or closed. If a single-bank PRECHARGE command is issued, tRP timing applies. tRPA (MIN) applies to all 8-bank DDR2 devices. 35. 34. 32. 33.
W3HG2128M72ACER-AD6
PRELIMINARY
Value is minimum pulse width, not the number of clock registrations. Applicable to Read cycles only. Write cycles generally require additional time due to Write recovery time (tWR) during auto precharge. tCKE (MIN) of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2* tCK + tIH. This parameter is not referenced to a specific voltage level, but specified when the device output is no longer driving (tRPST) or beginning to drive (tRPRE). When DQS is used single-ended, the minimum limit is reduced by 100ps.
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May 2006 Rev. 5
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W3HG2128M72ACER-AD6
PRELIMINARY
ORDERING INFORMATION FOR AD6
Part Number W3HG2128M72ACER806AD6xG** W3HG2128M72ACER665AD6xG** W3HG2128M72ACER534AD6xG W3HG2128M72ACER403AD6xG Speed/Data Rate 400MHz/800Mb/s 333MHz/667Mb/s 266MHz/533Mb/s 200MHz/400Mb/s CAS Latency 6 5 4 3 tRCD 6 5 4 3 tRP 6 5 4 3 Height* 18.29mm (0.72") TYP 18.29mm (0.72") TYP 18.29mm (0.72") TYP 18.29mm (0.72") TYP
** Contact factory for availability NOTES: * RoHS compliant product. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR AD6
Front View
133.35 (5.25)
3.00 (0.118)
18.29 (0.720) TYP
4.00 (0.157)
4.00 (0.157) 1.50 0.10 (0.059 0.004) 5.00 (0.196)
0.80 0.05 (0.031 0.002) 1.00 (0.039) 2.50 0.20 (0.098 0.007)
4.06 (0.160)
Back View
63.00 (2.48) 55.00 (2.165)
1.27 (0.050 -0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
May 2006 Rev. 5 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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W3HG2128M72ACER-AD6
PRELIMINARY
PART NUMBERING GUIDE
W 3 H G 2 128M 72 A C E R xxx AD6 x G
WEDC MEMORY (SDRAM) DDR 2 GOLD DUAL RANK DEPTH BUS WIDTH COMPONENT WIDTH x4 STACKED DIE BGA 1.8V REGISTERED SPEED (Mb/s) PACKAGE 240 PIN (.72) COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT
May 2006 Rev. 5
12
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White Electronic Designs
Document Title
W3HG2128M72ACER-AD6
PRELIMINARY
2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL,VLP
Revision History Rev #
Rev 0 Rev 1
History
Evaluation and review 1.1 Created concept data sheet
Release Date
July 2005 December 2005
Status
Concept Concept
Rev 2
2.1 Added ICC specs 2.2 Added AC specs
December 2005
Advanced
Rev 3 Rev 4
3.1 Moved to Preliminary 4.0 Updated package outline 4.1 Added "stacked die" designation "C" to part number and part number guide 4.2 Added new capacitance numbers.
January 2006 February 2006
Preliminary Preliminary
Rev 5
5.1 Corrected package width dimension
May 2006
Preliminary
May 2006 Rev. 5
13
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